1. Field of the Invention
This invention relates to a fuzzy cell structure for an electronic processor operating in a fuzzy logics mode.
More particularly, the invention relates to a processor of the type which comprises a fuzzyfication unit receiving a plurality of input variables on its input and being adapted to compute a membership value of such variables in a membership function, a processing unit connected downstream of the fuzzyfication unit to produce a fuzzy set, i.e. the results of a fuzzy logics inference operations performed on said plurality of variables, and a defuzzyfication unit operative to translate said inference results into a so-called crisp value.
2. Discussion of the Related Art
As is well known, electronic processors are currently available which operate in a general purpose fuzzy logics mode, and are sold under the trade name WARP 1-2-3.
These processors are directed to solve model and control problems in processes of significant complexity characterized by having several input variables, a few control variables, a particularly high dynamic range, and precision specifications which allow some latitude.
However, there are situations where these processors are not utilized to full capacity, such as where the number of the variables involved is small. In other situations, by contrast, these processors cannot be used due to their inherently inadequate speed and precision; this being the case, for instance, with the processing of digital signals and with the control problems brought about by a high dynamic range or the need for more accurate control actions.
For a better understanding of the invention aspects, the main rules of operation of the current-generation of fuzzy processors will be reviewed briefly. These processors are capable of processing rules of the following kind:
IF X.sub.1 is A.sub.ij and X.sub.2 is A.sub.2h and . . . THEN Y is C PA1 1) the sum of the membership functions through the universe of discourse is unity; PA1 2) at any point of the universe of discourse, there are only two membership functions with a non-zero degree of membership; PA1 3) the only aggregation operator used is the AND operator.
or variations of this same rule wherein the decision variables X, i.e. those appearing in the IF part or portion of the rule, are backed by a sub-set U.sub.i.OR right.R, A.sub.ij being one-dimension terms defined in U.sub.1.
The structure of these fuzzy processors can be represented schematically by three cascaded blocks, as shown in the appended FIG. 1.
A first "Fuzzyfication Unit" block is to translate, into linguistic terms, so-called `crisp` observations of the input variables X.sub.i by computing their membership value at each term. The membership values thus obtained are used by the "Computational Unit" to produce a fuzzy set, or term, representing the linguistic inference of the set of computed rules.
Rule processing is over once the linguistic inference is translated into a crisp value by a "Defuzzyfication Unit" block.
Further features of prior art fuzzy processors can be learned from European Patent Applications No. EP96830173.9 and EP96830090.5 by the Applicant, which are incorporated herein by reference.
An object of the invention is to provide a compact-size dedicated processor which has such structural and functional features that it can solve control problems involving few variables and still be sufficiently fast and accurate for use in the processing of digital signals.
This would allow certain limitations of conventional processors to be overcome.